The invention relates to a programmable 1-bit data processing arrangement which includes an ALU which is based on a 1-bit processing structure and a data memory which is realized as an end-around shift register having a word width of 1 bit, wherein data can be serially applied from data outputs to the ALU via unidirectional shift operations and the ALU applies data serially to the data memory via a common data input, and also relates to the problem of implementing simple, programmable logic which imposes only moderate requirements as regards data processing width and speed and in which a minimum number of gates is achieved by minimizing the requirements imposed on a universally programmable structure.
One-chip implementations which have a processing width of 1 bit are known. However, they utilize structures which internally have a structure for greater processing widths.
DE 38 24 306 A1 describes an arithmetic unit in which the data bus has a width of at least but preferably 1 bit and in which instructions and data are serially transported, via shift registers, between the data memory and the internal data bus of the microprocessor, so that the length of the individual data strings differs. The length of the data string to be transferred is indicated via a second line. The registers and also the arithmetic unit in this structure are designed for a multiple of the data bus width. The storage of the data then takes place in a RAM as in more complex structures. Mapping the data on a width of 1 bit is performed only for the data transfer between the RAM and the internal data bus of the processor; in this a shift register is used for the transfer.
GB 1 448 041 describes a 1-bit digital computer. The data is applied to the ALU via data buses having a width of 1 bit. The input data is applied to a register in parallel and the output data is output in parallel by an output register. The decoder accesses these registers via addresses and conducts the data sequentially to the RAM or to a working register connected to the ALU. A stack with four positions is used as the working register which is realized as a bi-directional shift register. In this case a simple sequencer is used which cyclically reads a fixed instruction sequence. In addition to the working register, this processor utilizes a RAM for storing intermediate results.
EP 0 428 326 A1 discloses a processor array system in which each ALU receives data from the data memory via a multiplexer and outputs data to the data memory via a multiplexer. Each individual ALU of this array system includes an accumulator register and a carry register which prepare data for the ALU. The input to the ALU from the accumulator register is multiplexed with an input from a shift register. This unidirectional shift register has a fixed length of 32 bits. It includes four data outputs which are all spaced 8 bits apart. One of these four inputs is selected and connected to the ALU via the multiplexer. The least significant bit of the shift register is linked to its most significant bit. In the case of bit-wise shift operations, each time one bit of this shift register is used as an operand for the ALU. In the case of multiplications the shift register supplies the operands and at the same time receives the multiplication result on the common data input.
For many applications it is not necessary to offer a large processing width, because the arriving data need not be processed very quickly or, because, due to the external process, so few data arrives that it can be serially processed also in the case of full functionality. Until now either over-sized chip structures with a higher power rating were used for these applications or recourse was taken to wired logic which, however, cannot be programmed.
In the field of smart cards however, there is a range of applications where the data throughput is not very high. Moreover, the width of the interface to the environment is fixed at 1 bit by the standardization of the contact interface ISO 7816-3.
Therefore, it is an object of the invention to provide a programmable structure which operates with a processing width of 1 bit, occupies an as small as possible surface area and satisfies simple requirements such as communication and processing of data.
This object is achieved according to the invention in that the shift register can be partitioned, that, once selected by a selection instruction, an active partition remains active until a further selection instruction activates another partition, and that data can be applied to the ALU from the data output at the end of the partition and data can be applied from the ALU to the data input of the partition at the beginning of the partition.
For the programmable structure with a processing width of 1 bit the invention utilizes the fact that for smart cards and identification systems the communication interface is standardized in conformity with ISO7816-3 which specifies the 1-bit data width and that, using a reduced instruction set, there is obtained a universally programmable, operational structure which requires a minimum chip surface area only.
The end-around shift register can be partitioned into partitions by way of select instructions or fixed presets; the lengths of the partitions may then be different.
This structure is optimized in that use is made of only two 1-bit working registers which are connected in series, the value of the second working register containing the previous value of the first working register. Generally speaking, the ALU supplies the first working register with values other than those applied to the shift register. Commonly used instructions consist of 1-bit sequences. Because the ALU simultaneously outputs different values to its working register and to the shift register, a higher calculation capability is achieved while using as few means as possible. Moreover, the selected partition can be closed so as to form a ring, via the ALU, so that its contents are restored again after complete reading out and shifting through.
The data of the variables stored in the relevant partition is serially applied to the ALU via the data output at the partition end. Results of completed arithmetic operations are serially applied, in the same shift operation, to the data input at the beginning of the relevant active partition.
An end-around shift register is used to generate the addresses for the program memory instead of a complex address counter. As a result, the address sequences are not linear and the next address is generated by means of the previous address.
Call structures are dispensed with; this must be taken into account for the programming of this structure. Several registers otherwise required can thus be dispensed with, so that a simple structure is obtained not only for the ALU but also for the control system. However, only conditional jumps can be programmed; in given circumstances individual program sequences are then possibly completed several times.
The entire system can be adapted to relevant applications by extensions or also by reduction of components, the processing width of 1 bit nevertheless being maintained. When the partitioning is permanently adjusted, the partitioning logic can be dispensed with. A further set of instructions can be prepared by extension of the program memory.
The power consumption can be further reduced when this structure operates with asynchronous logic.
The following sub-objects, required for the use of such systems, are achieved by means of this system.
comparison with n-bit constant,
addition of constants to variables,
negation of the bits of a byte,
copying of a single bit from a bit sequence,
setting of a single bit from the bit sequence to a corresponding value,
storing of individual bits and bit sequences,
shift register of variable length for encoding algorithm,
serial input and output of one or more bits,
conditional jumps,
addition and subtraction of bit sequences,
logic function with each time 2 bits.
The set of instructions of the design used represents a processor instruction set which includes 16 ALU instructions and utilizes only two working registers. Consequently, complex algorithms can also be executed by means of this simple but efficient arithmetic unit.
The advantage of this structure resides in the drastically reduced chip surface area, so that, in addition to the required space and materials, the power consumption is also reduced. The described requirements enable implementation of a plurality of applications which do not impose severe requirements as regards data width and processing speed. Because of its moderate surface area requirements, this universally programmable structure can be simply integrated in circuits, without an additional chip being required.